This application claims the benefit of priority to Japanese Patent Application No. 8-11029, filed Jan. 25, 1996, which is incorporated by reference.
The present invention relates to a method for testing a semiconductor memory which uses redundancy technology, and also to an apparatus designed to test that memory.
Most of the semiconductor devices manufactured at the present time adopt redundancy technology. The adoption of this technology is intended to increase the number of good products manufactured. The redundancy technology is directed to a technique for replacing defective memory cells or defective rows/columns of a main cell array with spare rows/columns. The redundancy technology is useful in remedying defective semiconductor devices, and therefore contributes to an increase in the manufacturing yield of semiconductor memories.
A test for testing a semiconductor device which uses redundancy technology includes three testing items, namely, a DC characteristic test, a function (FNC) test, and redundancy (R/D) analysis. The DC characteristic test is a test for checking the DC characteristic of a semiconductor memory. The FNC test is a test for checking the functions of the semiconductor memory. In the R/D analysis, the location of a defective portion of a main memory cell array is checked on the basis of the results of the FNC test, and an arithmetic operation for replacing the memory cell and row/column at the defective portion with a spare row/column is executed on the basis of the replacement program.
FIG. 1 is a block circuit diagram showing a conventional semiconductor memory tester.
Referring to FIG. 1, the memory tester comprises a memory testing unit 100, an operation terminal 101 for operating the memory testing unit 100, and a test station 150 where a wafer is placed for test. The memory testing unit 100 includes a CPU 102, a main memory 103 which stores a test program (TEST PRG.) and OS, and further stores a replacement program (R/D PRG) used in the arithmetic operation for replacement, a DC characteristic/function tester which outputs test patterns (1) and (2) and an expected value (3), a determination device 105 which compares the expected value (3) with a response signal (4) supplied from a DUT (not shown), determines whether or not the response signal represents a normal state, and supplies determination information (5) to the CPU 102, and a fail memory 107 which stores information (6) regarding the occurrence of an abnormal state when abnormality is detected with respect to the DUT. In FIG. 1, reference numeral (9) denotes control information issued by CPU 102.
The memory tester mentioned above executes a DC characteristic test and an FNC test with respect to the DUT in accordance with the test program. If an abnormal state is detected with respect to the DUT in the test, the information (6) regarding the occurrence of the abnormal state is stored in the fail memory 107.
After the DC characteristic test and the FNC test, the R/D analysis is executed on the basis of the test program. In this analysis, information (7) representing the location of a defective portion of the main memory cell array is extracted from information (6) and read out from the fail memory 107. An operation unit (not shown), included in the CPU 102, analyzes the readout information (7) in accordance with the replacement program and carries out the operation for replacing the defective portion with a spare row/column. Results of this replacement operation (i.e., replacement information RPLC DATA) are used in the redundancy step to check which fuse should be blown by a laser blower. The results of the replacement operation are stored in a storing medium, such as a floppy disk, by means of the operation terminal 101.
The memory tester shown in FIG. 1 serially executes the DC characteristic test, the FNC test, and the R/D analysis. The reason for the serial execution is that the operations described in the test program are executed by a single CPU (CPU 102).
An increase in the memory capacity entails an increase in the number of memory cells, and results in miniaturization of memory cells. In addition, since the internal wiring is of a multi-level structure, the manufacturing process is complicated, accordingly. As shown in FIG. 2, the number of defective memory cells increases in accordance with an increase in the memory capacity. In order to reliably remedy the defective memory cells, the number of spare rows/columns is also increasing, as shown in FIG. 3.
An increase in the memory capacity entails not only an increase in the number of memory cells but also an increase in the number of peripheral circuits, such as row/column decoders. Accordingly, the time needed for testing one DUT is inevitably long.
FIG. 4 shows the relationships between the total test time for one DUT and the memory capacity. FIG. 5 shows the relationships between the total test time for one wafer and the memory capacity. In preparing the data shown in FIG. 5, it was assumed that the total test time for one wafer was equal to the total length of time of the test times for four DUTs. (In actuality, 80 to 130 DUTs correspond to one wafer. Since all DUTs cannot be depicted, they are compressed into four DUTs, for simplicity.)
As shown in FIG. 4, an increase in the test time for one DUT does not become a problem when the memory capacity changes from xe2x80x9c1MDRAMxe2x80x9d to xe2x80x9c4MDRAMxe2x80x9d. However, when the memory capacity changes from xe2x80x9c4MDRAMxe2x80x9d to xe2x80x9c16MDRAMxe2x80x9d, the total test time poses a poor throughput problem since it is about twice as long as the total test time of the case of xe2x80x9c1MDRAMxe2x80x9d. To solve this problem, a technique referred to as xe2x80x9cmulti-probingxe2x80x9d is employed to shorten the total test time. The xe2x80x9cmulti-probingxe2x80x9d is specifically a method in which a plurality of DUTs are tested at one time. In FIG. 5, the data corresponding to xe2x80x9c16MDRAMxe2x80x9d is data obtained when two DUTs are tested at one time. In comparison with the case of xe2x80x9csingle-probingxe2x80x9d (indicated by line I in FIG. 5) where DUTs are tested one by one, the use of the xe2x80x9cmulti-probingxe2x80x9d technique is advantageous in that the total test time required is half. The use of the xe2x80x9cmulti-probingxe2x80x9d technique is advantageous to a certain degree when the memory capacity changes from xe2x80x9c16MDRAMxe2x80x9d to xe2x80x9c64MDRAMxe2x80x9d. However, when the memory capacity advances to xe2x80x9c256MDRAMxe2x80x9d, the total test time is about twice as long as that of the case of xe2x80x9c16MDRAMxe2x80x9d, as indicated by line II. This being so, it is generally thought that the xe2x80x9cexpansion of multi-probingxe2x80x9d is tried when 256MDRAMs are mass-produced. The xe2x80x9cexpansion of multi-probingxe2x80x9d is to increase the number of DUTs tested at one time. For example, the number of DUTs tested at one time is increased from xe2x80x9c32xe2x80x9d to xe2x80x9c64xe2x80x9d. The use of the xe2x80x9cexpansion of multi-probingxe2x80x9d shortens the total test time.
The ultimate purpose of the multi-probing is to test all DUTs on a wafer. However, in the cases where the memory capacity is greater than xe2x80x9c256MDRAMxe2x80x9d, there are no DUTs that can be tested at one time, as shown in FIG. 5. In such cases, a decrease in the total test time required for one wafer does not result in any advantage. The total test time for one wafer increases, depending upon the total test time for one DUT.
After the expansion of multi-probing does not produce any advantage, the technique which is available for improving the throughput is merely to increase the number of memory testers employed, thereby enhancing the throughput of the production lines system per unit time.
However, the adoption of this technique is disadvantageous in that a large number of costly memory testers are newly required and that the existing production lines have to be modified or new production lines have to be installed. Such facility investment greatly increases the manufacturing cost of one semiconductor memory device.
In recent years, a new testing method is proposed wherein the DC characteristic test and FNC test for a DUT are executed independently of the R/D analysis.
This proposal is made, for example, in xe2x80x9cGuidebook on Apparatuses for Manufacturing And Testing Apparatusesxe2x80x9d, Kogyo Chosakai, 1996 and Tsunehiro Satou et al., xe2x80x9cTester for Memoriesxe2x80x9d, Dec. 4, 1995, Page 152, From Left Column, Line 30 to Right Column, Line 12.
FIG. 6 is a block circuit diagram showing an example of a memory tester which executes the R/D analysis independently of the D/C characteristic test and the FNC test. FIG. 7 is a graph showing the data obtained by the memory tester shown in FIG. 6, and the data in the graph represents the relationships between the total test time for one wafer and the memory capacity. In FIG. 6, the same reference numerals as in FIG. 1 are used to denote corresponding structural elements. In preparing the data shown in FIG. 7, it was assumed that the total test time for one wafer was equal to the total length of time of the test times for four DUTs, as in the data shown in FIG. 5.
As can be seen from the data corresponding to xe2x80x9c1MDRAMxe2x80x9d in FIG. 7, the DC characteristic test and FNC test are first performed for DUT1, and then the R/D analysis is executed by use of a device designed exclusively for R/D analysis. To cope with these procedures, the CPU 102 of the memory tester shown in FIG. 6 reads out information (7) indicative of the location of a defective portion of the main memory cell array from the fail memory 105, and supplies the readout information (7) to device 151 designed exclusively for R/D analysis. Device 151 analyzes the information (8) received from the CPU 102 on the basis of the replacement program (R/D PRG.), and executes an arithmetic operation for using spare rows/columns for replacement. When the R/D analysis is being executed, the memory tester shown in FIG. 6 performs the DC characteristic test and the FNC test with respect to the next DUT2. Results (RPLC DATA) of the arithmetic operation performed by device 151 are fed back to the CPU 102.
The new testing method mentioned above is advantageous in that the R/D analysis for DUT1 is allowed to overlap with the test for DUT2, and the R/D analysis for DUT2 is likewise allowed to overlap with the test for DUT3, as can be seen in FIG. 7. As a result, the total test time is shorter than that of the case indicated by line III (FIG. 5) by the time corresponding to the sum of the overlapping times.
As can be seen from FIG. 7, the R/D analysis time becomes markedly long in accordance with an increase in the memory capacity. This is because the arithmetic operation for remedying the defective memory cells becomes more complex in accordance with an increase in the number of defective memory cells and the number of spare rows/columns. In regard to the testing method, it can be pointed out that the total testing time can be shortened in accordance with an increase in the R/D analysis time.
According to the testing method, however, the R/D analysis for the last DUT does not overlap with the test for another DUT. Accordingly, the total test time for one wafer is lengthened by the time corresponding to the R/D analysis time for the last DUT.
In regard to the testing method, it should be also noted that the total test time cannot be shortened at all if the ultimate purpose of the multi-probing is attained (i.e., if all DUTs on the wafer can be tested at one time). This is due to the absence of the overlap time, and the phenomenon is shown in the data corresponding to the memory capacity of xe2x80x9c256Mxe2x80x9d or higher. That is, the advantage of the testing method is no longer available in the case where the ultimate purpose of the multi-probing is attained, and the total test time for one wafer continues to increase, depending upon the test time for one DUT.
A method for testing a semiconductor device according to an aspect of the present invention comprises: executing a function test on the semiconductor device; executing a DC characteristic test on the semiconductor device; executing a remedy determination process of the semiconductor device, said remedy determination process being performed in parallel to the DC characteristic test; and executing a remedy process on the semiconductor device.